An increasingly popular application of a field programmable gate array (FPGA) is the debug and functional verification of an application specific integrated circuit (ASIC) design through hardware emulation. In an emulation application, the user can perform a series of operations, such as a series of random access memory (RAM) operations, and then stop the dock to dump out register and memory contents for debug and analysis. Such an operation is referred to as readback capture. With respect to a RAM in the FPGA, readback capture is the process of cycling through addresses of the RAM and reading out the data, which eventually propagates to the bitstream. A user can analyze the output bitstream to interpret and reveal the contents of the RAM at each address.
Readback capture of a RAM in a programmable IC, such as an FPGA, can be affected by dock glitches, as well as loss of user data. To avoid these problems, non-ideal constraints are imposed on the user and the user design being emulated. It is desirable to perform readback capture of a RAM in a programmable IC that avoids both clock glitches and loss of user data.